1. Field
Exemplary embodiments of the present invention relate to a method for operating a non-volatile memory device, and more particularly, to a method for operating a non-volatile memory device including an erase operation and a Soft program-On-Chip (SOC) operation.
2. Description of the Related Art
A non-volatile memory device is a memory device capable of retaining stored data although power is turned off.
A non-volatile memory device may perform a program operation, an erase operation, and a read operation. In particular, a NAND-type non-volatile memory device performs a program operation and an erase operation by injecting or discharging charges to or from a floating gate electrode through Fowler-Nordheim (F-N) tunneling. In a NAND-type non-volatile memory device, programmed memory cells have a positive (+) threshold voltage, and erased memory cells have a negative (−) threshold voltage. As the range of threshold voltage distribution is narrower, the operation characteristics of a memory device are improved.
Hereafter, a conventional non-volatile memory device and an operation method thereof are described with reference to the accompanying figures.
FIG. 1 illustrates a structure of a conventional non-volatile memory device.
Referring to FIG. 1, the non-volatile memory device includes a memory block 100, a block switch 110, a high-voltage switch 120, a bulk voltage generator 130, and a page buffer 140.
The memory block 100 includes a plurality of memory cells MC for storing data, a plurality of word lines WL0 to WLN that select and enable a memory cell MC, and a plurality of bit lines BL0 to BLM that output the data of the memory cells MC. The word lines WL0 to WLN are in parallel to each other, and the bit lines BL0 to BLM are in parallel to each other as well. The bit lines BL0 to BLM may cross the word lines WL0 to WLN. In the memory block 100, the memory cells MC are serially coupled between a source selection transistor SST and a drain selection transistor DST to form a string structure. One end of each string is coupled with a corresponding bit line BL0 to BLM, while the other end of the string is coupled with a common source line CSL in parallel. The gates of a plurality of drain selection transistors DST are coupled with a drain selection line DSL, and the gates of a plurality of source selection transistors SST are coupled with a source selection line SSL. Also, the gates of the memory cells MC are coupled with the word lines WL0 to WLN, and a set of memory cells coupled with the same word line is called a page.
The block switch 110 is selected by a selection signal SELb, and the block switch 110 may enable the high-voltage switch 120 by driving a node BLKWL into a high level based on the selection signal SELb.
The high-voltage switch 120 includes a plurality of high-voltage transistors SHT, HT and DHT, and the high-voltage switch 120 controls the connection between global word lines GWL0 to GWLN and local word lines WL0 to WLN according to the level of the node BLKWL. In particular, during an erase operation, the high-voltage switch 120 couples the global word lines GWL0 to GWLN that are coupled with a ground voltage with the local word lines WL0 to WLN to apply the ground voltage to the local word lines WL0 to WLN.
The bulk voltage generator 130 generates a bulk voltage VBK according to a program/erase/read operation and applies the generated bulk voltage VBK to a bulk of the memory block 100, for example, a P-well. In particular, during an erase operation, the bulk voltage generator 130 generates a high voltage and applies the generated high voltage to the bulk of the memory block 100. The high voltage applied to the bulk during an erase operation is referred to as an erase voltage.
The page buffer 140 includes a plurality of page buffer circuits (not shown). The page buffer 140 performs a program operation or a read operation by being coupled with a bit line BL. Further description of the structure and operation of the page buffer is omitted.
FIG. 2 is a flowchart describing a method for operating a conventional non-volatile memory device. Specifically, the figure describes an erase operation and a Soft program-On-Chip (SOC) operation.
First, when an erase command and an address that designates a target memory block 100 to be erased are inputted to a decoder in step S210, a corresponding block switch 110 is selected, and the high-voltage switch 120 is enabled to apply a ground voltage to all the word lines WL0 to WLN of the memory block 100 based on the output of the block switch 110.
Subsequently in step S220, an erase voltage is generated by the bulk voltage generator 130 and applied to the bulk of the memory block 100, and accordingly, the data stored in the memory cells MC of the corresponding memory block 100 are erased.
In step S230, the page buffer 140 performs a read operation and verifies whether the data of all the memory cells MC of the corresponding memory block 100 are erased.
If any of the data of the memory cells MC is not erased, the verification step determines that the erase operation was to be a failure, and the process of the step S220 is repeated.
Otherwise, when the data of all the memory cells MC are erased, more specifically, when the erase operation is decided to be a success, the erase operation ends and the method moves to step 240 to perform a Soft program-On-Chip (SOC) operation.
More specifically, when the erase operation ends, the SOC operation is performed in step S240 by applying a soft program voltage to the word lines WL0 to WLN while applying a ground voltage to the bulk of the memory block 100.
Subsequently in step S250, the SOC operation is verified based on an SOC verification voltage. More specifically, the SOC verification voltage is a negative voltage ranging from approximately −1V to approximately −2V. The SOC operation verification step determines whether there is a memory cell MC whose threshold voltage is equal to or exceeds the SOC verification voltage.
The SOC operation verification is performed for each string. If there is a memory cell whose threshold voltage is increased to the SOC verification voltage among the memory cells MC of a particular string, the string is decided to have succeeded in the SOC operation, and the string is referred to as a ‘pass string.’ Conversely, if there is no memory cell whose threshold voltage is equal to or exceeds the SOC verification voltage among the memory cells MC of a particular string, the string is decided to have failed in the SOC operation, and the string is referred to as a ‘non-pass string.’
When the number of pass strings reaches a predetermined number X after performing the SOC operation verification onto all strings, the SOC operation is decided to be successful and the SOC operation is ended.
Conversely, when the number of pass strings does not reach a predetermined number X, the SOC operation is decided to have failed and the operation of the step S240 is repeated by increasing the SOC operation voltage. While performing the operation of the step S240 again, the threshold voltage of the memory cells of pass strings is prevented from being varied while the SOC operation voltage is applied by applying a bit line program prevention voltage, e.g., a power source voltage Vcc, to the bit lines coupled to the pass strings. On the other hand, the threshold voltage of the memory cells of the non-pass strings is increased while the SOC operation voltage is applied by applying a bit line program voltage, e.g., 0V, to the bit lines coupled to the non-pass strings.
FIG. 3 illustrates the effects of the method for operating the conventional non-volatile memory device.
Referring to FIG. 3, a curve E2 indicates the threshold voltage distribution of memory cells MC whose SOC operation ends and a curve E1 indicates the threshold voltage distribution of memory cells MC whose erase operation ends. The curve E2 is shifted to the right when compared with the curve E1. The shifting of curve E2 to the right signifies that the threshold voltage of the memory cells is raised through the SOC operation.
Other than increasing in the threshold voltage, the SOC operation decreases the range W1 of the threshold voltage distribution of memory cells, but only to a limited extent. The threshold voltage distribution after an SOC operation decreases only a limited amount because each of the memory cells has diverse characteristics, such as having different threshold voltage according to the position. Also, when the threshold voltage of any one cell among the memory cells MC reaches the verification voltage, the SOC operation ends.
As described above, when the range W1 of the threshold voltage distribution of the memory cells MC is wide, the range PV1, PV2 and PV3 of the threshold voltage distribution of the memory cells MC in the program state becomes wide as well. Accordingly, the margin between the levels is decreased in multi-level cells.